covered - Verilog code coverage analyzer
| Website: | http://covered.sourceforge.net/ |
|---|---|
| License: | GPLv2+ |
| Vendor: | Fedora Project |
- Description:
Covered is a Verilog code-coverage utility using VCD/LXT style dumpfiles and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage reports. Covered also contains a built-in race condition checker and GUI report viewer.
Packages
| covered-0.7.7-1.el6.src [3.0 MiB] |
Changelog
by Chitlesh Goorah (2009-11-17):
- Initial package for fedora. |