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4 I/P AND gate designed with large (v0 version) and small (v4 version) input stages. The stage effort is 1.6 for the an4v0x05, is 1.9 for the an4v0x1, 2.2 for the an4v0x2, 2.6 for the an4v0x4 and 4.0 for the an4v4x1. The cells use a P/N ratio of about 2.5 for the NAND gates. The v0 cells are optimised for speed with typical wireload values, while the v4 cells are optimised for a zero wireload capacitance.
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