na4 standard cell family
4-I/P NAND gate
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The na4_x1 is a single stage 4-NAND with P/N ratio of about 3. The na4_x4 is a 3 stage 4-NAND with stage efforts of about 1.2 and 3.9.
nq:(i0*i1*i2*i3)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i3
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
na4_x1
2.0
60
3.30
1.16
14.3
5.4f
59
2.97
51
3.26
na4_x4
3.3
100
5.50
2.89
65.1
5.7f
164
0.74
184
0.57
na4_x1
Effort
FO4
Log.
i0
/\
1.92
1.83
¯_
i1
/\
1.94
1.98
¯_
i2
/\
1.85
1.97
¯_
i3
/\
1.74
1.93
¯_
na4_x4
Effort
FO4
Log.
i0
/\
2.99
0.43
¯_
i1
/\
2.93
0.45
¯_
i2
/\
2.82
0.44
¯_
i3
/\
2.70
0.44
¯_
Web data book for the sxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 08 JUL 2007