a2 standard cell family
2-I/P AND gate
UP
PREV
NEXT
2 I/P AND gate with a stage effort of about 1.8 for the a2_x2 and about 3.6 for the a2_x4.
q:(i1*i0)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i0
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
a2_x2
1.7
50
2.75
1.16
31.7
5.4f
73
1.48
101
1.14
a2_x4
2.0
60
3.30
2.08
48.4
5.2f
89
0.74
126
0.57
a2_x2
Effort
FO4
Log.
i0
/\
¯_
1.64
i1
/\
¯_
1.79
a2_x4
Effort
FO4
Log.
i0
/\
¯_
1.72
i1
/\
¯_
1.83
Web data book for the sxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 08 JUL 2007