nd2a standard cell family
2-I/P NAND gate with inverted input
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Single stage 2-I/P NAND gates with one inverted input. 2 drive strengths with a P:N ratio of 2.
z:(a+b')
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
b
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nd2a_x1
1.7
50
2.75
1.00
8.2
4.2f
45
2.96
36
2.16
nd2a_x2
1.7
50
2.75
1.92
14.6
7.6f
44
1.52
34
1.11
nd2a_x1
Effort
FO4
Log.
a
/\
¯_
1.68
b
/\
1.19
1.24
¯_
nd2a_x2
Effort
FO4
Log.
a
/\
¯_
1.54
b
/\
1.13
1.16
¯_
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 28 MAY 2007