ao22 standard cell family
2-OR into 2-AND gate
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2-1 I/P OR-AND gate with stage efforts of about 3.5 for pins
i0
and
i1
and 2.6 for pin
i2
of the ao22_x2, and about 7 for pins
i0
and
i1
and 5.2 for pin
i2
of the ao22_x4.
q:((i0+i1)*i2)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i1
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
ao22_x2
2.0
60
3.30
1.27
29.6
3.8f
109
1.53
146
1.23
ao22_x4
2.7
80
4.40
1.96
45.2
3.6f
138
0.77
190
0.63
ao22_x2
Effort
FO4
Log.
i0
/\
¯_
2.27
i1
/\
¯_
2.12
i2
/\
¯_
1.94
ao22_x4
Effort
FO4
Log.
i0
/\
¯_
2.64
i1
/\
¯_
2.48
i2
/\
¯_
2.12
Web data book for the ssxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 16 JUL 2007