no4 standard cell family

4-I/P NOR gate
no4 symbol
The no4_x1 is a single stage 4-NOR with P/N ratio of 1.1. The no4_x4 is a 3 stage 4-NOR with stage efforts of about 1.4 and 3.9.
nq:(i3+i2+i0+i1)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
no4_x1 2.0  60 3.30  0.92  12.7  5.5f  64  6.16  49  2.31
no4_x4 3.3 100 5.50 2.66  61.6  5.9f 198  0.76 157  0.61
no4_x1
 
Effort
FO4 Log.
i0 /\ 2.48 2.76
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i1 /\ 2.15 2.72
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i2 /\ 2.70 2.83
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i3 /\ 2.75 2.78
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no4_x1 schematic no4_x1 standard cell layout
no4_x4
 
Effort
FO4 Log.
i0 /\ 3.09 0.46
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i1 /\ 2.76 0.47
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i2 /\ 3.32 0.47
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i3 /\ 3.42 0.47
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no4_x4 schematic no4_x4 standard cell layout