nr2a standard cell family
2-I/P NOR gate with inverted input
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Single stage 2-I/P NOR gates with one inverted input. The output P:N ratio is about 0.77 and the stage effort on pin
a
is 1.2.
z:(a*b')
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
a
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nr2av0x1
2.7
64
3.52
1.22
29.1
5.6f
80
4.49
76
1.30
nr2av0x1
Effort
FO4
Log.
a
/\
¯_
2.04
b
/\
1.43
1.69
¯_
Web data book for the vgalib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 06 JUL 2007