aoi22 standard cell family

2×2-AND into 2-NOR gate
aoi22 symbol
3 cells with different drive strengths, each with a P/N ratio of about 2. The Ramp Rise time reported below is an average of when one or the other or both of the P-transistors connected to a1 and a2 are on. The Synopsys Liberty format .lib file has the precise timing for each case.
z:((a1*a2)+(b1*b2))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
aoi22_x05 2.0  60 3.30  0.67   8.7  3.5f  55  5.32  50  4.09
aoi22_x1 2.0  60 3.30 1.29  14.9  6.0f  52  2.72  47  2.17
aoi22_x2 3.7 110 6.05 2.47  27.8 11.2f  51  1.44  46  1.12
aoi22_x05
 
Effort
FO4 Log.
a1 /\ 2.09 1.93
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a2 /\ 2.07 1.96
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b1 /\ 1.79 2.01
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b2 /\ 1.68 1.90
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aoi22_x05 schematic aoi22_x05 standard cell layout
aoi22_x1
 
Effort
FO4 Log.
a1 /\ 1.95 1.77
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a2 /\ 1.91 1.76
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b1 /\ 1.61 1.76
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b2 /\ 1.54 1.69
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aoi22_x1 schematic aoi22_x1 standard cell layout
aoi22_x2
 
Effort
FO4 Log.
a1 /\ 1.88 1.70
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a2 /\ 1.86 1.71
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b1 /\ 1.52 1.62
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b2 /\ 1.51 1.66
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aoi22_x2 schematic aoi22_x2 standard cell layout