oa22 standard cell family
2-AND into 2-OR gate
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2-1 I/P AND-OR gate with stage efforts of about 3.5 for pins
i0
and
i1
and 2.9 for pin
i2
of the oa22_x2, and about 7 for pins
i0
and
i1
and 5.7 for pin
i2
of the oa22_x4.
q:((i0*i1)+i2)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i1
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
oa22_x2
2.0
60
3.30
1.16
30.7
4.2f
109
1.49
144
1.18
oa22_x4
2.7
80
4.40
1.85
47.1
4.0f
138
0.75
188
0.61
oa22_x2
Effort
FO4
Log.
i0
/\
¯_
2.16
i1
/\
¯_
2.12
i2
/\
¯_
2.21
oa22_x4
Effort
FO4
Log.
i0
/\
¯_
2.53
i1
/\
¯_
2.48
i2
/\
¯_
2.43
Web data book for the sxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 08 JUL 2007