xaon22 standard cell family

2-I/P exclusive OR gate with 2×2-AND inputs
xaon22 symbol
2 XOR gates with each input being a 2-AND gate, designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1*a2)^(b1*b2)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xaon22_x05 3.3 100 5.50  0.75  27.0  4.5f 101  4.66  96  3.61
xaon22_x1 3.3 100 5.50 1.26  43.5  8.0f  92  2.71  86  1.87
xaon22_x05
 
Effort
FO4 Log.
a1 /\ 2.09 1.70
¯_ 2.80
a2 /\ 2.12 1.81
¯_ 2.85
b1 /\ 2.71 3.35
¯_ 2.50
b2 /\ 2.74 3.33
¯_ 2.50
xaon22_x05 schematic xaon22_x05 standard cell layout
xaon22_x1
 
Effort
FO4 Log.
a1 /\ 2.04 1.78
¯_ 2.63
a2 /\ 2.02 1.83
¯_ 2.63
b1 /\ 2.40 2.82
¯_ 2.21
b2 /\ 2.40 2.78
¯_ 2.20
xaon22_x1 schematic xaon22_x1 standard cell layout