nd3 standard cell family

3-I/P NAND gate
nd3 symbol
The P:N ratio is set to 2.33. The fastest speed occurs when the shape factor r=√(KP÷KN×µ). For a 3-NAND gate, KP=1; KN=7/3, and for µ=9/4, r=√(27/28). We chooose to set r=1 instead, so the P:N ratio is close to the maximum speed, as well as giving balanced rise and fall drive strengths, with the P and N transistors having the same size.
z:(a*b*c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd3_x05 1.7  50 2.75  0.55   7.3  2.9f  54  4.95  43  4.24
nd3_x1 1.7  50 2.75  0.92  11.2  4.5f  52  2.96  41  2.54
nd3_x2 1.7  50 2.75 1.52  17.0  7.0f  50  1.80  39  1.54
nd3_x4 3.0  90 4.95 3.05  52.9 15.0f  63  0.90  42  0.77
nd3_x05
 
Effort
FO4 Log.
a /\ 1.61 1.58
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b /\ 1.55 1.58
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c /\ 1.46 1.57
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nd3_x05 schematic nd3_x05 standard cell layout
nd3_x1
 
Effort
FO4 Log.
a /\ 1.54 1.50
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b /\ 1.45 1.45
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c /\ 1.36 1.43
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nd3_x1 schematic nd3_x1 standard cell layout
nd3_x2
 
Effort
FO4 Log.
a /\ 1.46 1.41
¯_
b /\ 1.39 1.38
¯_
c /\ 1.30 1.35
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nd3_x2 schematic nd3_x2 standard cell layout
nd3_x4
 
Effort
FO4 Log.
a /\ 1.25 1.29
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b /\ 1.38 1.40
¯_
c /\ 1.46 1.45
¯_
nd3_x4 schematic nd3_x4 standard cell layout