xnr2 standard cell family

2-I/P exclusive NOR gate
xnr2 symbol
2 XNOR gates designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:(a^b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xnr2_x05 2.3  70 3.85  0.67  19.1  3.9f  86  4.84  82  3.69
xnr2_x1 2.3  70 3.85 1.22  32.8  6.4f  83  2.62  79  2.06
xnr2_x05
 
Effort
FO4 Log.
a /\ 1.75 1.55
¯_ 2.56
b /\ 2.13 2.68
¯_ 2.48
xnr2_x05 schematic xnr2_x05 standard cell layout
xnr2_x1
 
Effort
FO4 Log.
a /\ 1.65 1.40
¯_ 2.39
b /\ 1.99 2.52
¯_ 2.27
xnr2_x1 schematic xnr2_x1 standard cell layout