inv standard cell family
inverter
UP
PREV
NEXT
4 inverters with P/N ratios of 2 (inv_x1, inv_x8), 1.5 (inv_x2) and 1.7 (inv_x4). The inv_x2 is considered as the reference inverter for logical effort calculations.
nq:i'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
inv_x1
1.0
30
1.65
0.35
6.5
3.8f
42
2.96
38
2.27
inv_x2
1.0
30
1.65
0.58
9.6
6.0f
42
1.97
33
1.14
inv_x4
1.3
40
2.20
1.36
16.4
12.0f
38
0.87
32
0.56
inv_x8
2.3
70
3.85
2.77
35.2
25.1f
37
0.37
33
0.28
inv_x1
Effort
FO4
Log.
i
/\
1.14
1.16
¯_
inv_x2
Effort
FO4
Log.
i
/\
1.06
1.07
¯_
inv_x4
Effort
FO4
Log.
i
/\
0.99
1.00
¯_
inv_x8
Effort
FO4
Log.
i
/\
0.97
0.95
¯_
Web data book for the sxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 08 JUL 2007