a3 standard cell family
3-I/P AND gate
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3 I/P AND gate designed with a stage effort of about 2.1 for the a3_x2 and about 4.2 for the a3_x4.
q:(i0*i1*i2)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i2
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
a3_x2
2.0
60
3.30
1.62
40.0
5.2f
102
1.53
128
1.22
a3_x4
2.3
70
3.85
2.31
55.7
5.1f
128
0.77
150
0.61
a3_x2
Effort
FO4
Log.
i0
/\
¯_
1.84
i1
/\
¯_
1.96
i2
/\
¯_
2.05
a3_x4
Effort
FO4
Log.
i0
/\
¯_
1.99
i1
/\
¯_
2.10
i2
/\
¯_
2.18
Web data book for the ssxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 16 JUL 2007