ao2o22 standard cell family

2×2-OR into 2-AND gate
ao2o22 symbol
2-2 I/P OR-AND gate with a stage effort of about 3.5 for the ao2o22_x2, and about 7 for the ao2o22_x4.
q:((i2+i3)*(i0+i1)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
ao2o22_x2 3.0  90 4.95 1.39  32.4  4.3f 112  1.49 156  1.19
ao2o22_x4 3.3 100 5.50 2.08  50.2  4.1f 140  0.75 202  0.62
ao2o22_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.35
i1 /\
¯_ 2.24
i2 /\
¯_ 2.52
i3 /\
¯_ 2.69
ao2o22_x2 schematic ao2o22_x2 standard cell layout
ao2o22_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.73
i1 /\
¯_ 2.60
i2 /\
¯_ 2.88
i3 /\
¯_ 3.05
ao2o22_x4 schematic ao2o22_x4 standard cell layout