nd2 standard cell family
2-I/P NAND gate
UP
PREV
NEXT
Single stage 2-I/P NAND gates with
x2
and
x4
drive strengths and a P:N ratio of about 2.4. The
nd2v6x4
is a layout variant of the
nd2v0x4
.
z:(a*b)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
b
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nd2v0x2
1.3
32
1.76
0.81
9.5
4.9f
43
2.27
37
2.04
nd2v0x4
2.7
64
3.52
1.62
17.6
9.7f
42
1.13
36
1.02
nd2v6x4
2.7
64
3.52
1.62
17.8
9.5f
42
1.13
36
1.02
nd2v0x2
Effort
FO4
Log.
a
/\
1.22
1.24
¯_
b
/\
1.18
1.23
¯_
nd2v0x4
Effort
FO4
Log.
a
/\
1.21
1.22
¯_
b
/\
1.15
1.21
¯_
nd2v6x4
Effort
FO4
Log.
a
/\
1.22
1.23
¯_
b
/\
1.14
1.19
¯_
Web data book for the vgalib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 06 JUL 2007