mxi2 standard cell family
Inverting 2-way multiplexers
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This two-way inverting mux uses a CMOS transfer gate for the fastest speed.
z:((a0*s')+(a1*s))'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
a0
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
mxi2v2x1
4.0
96
5.28
1.52
20.9
5.0f
91
4.49
50
2.08
mxi2v2x1
Effort
FO4
Log.
a0
/\
1.95
1.92
¯_
a1
/\
1.94
1.95
¯_
s
/\
2.71
4.21
¯_
2.86
Web data book for the vgalib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 06 JUL 2007