oan22 standard cell family
2×2-OR into 2-AND gate
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2 cells with different drive strengths, each with a P/N ratio of about 2. The oan22_x1 has a stage effort of about 1.7 and the oan22_x2 about 2.2.
z:((a1+a2)*(b1+b2))
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
b2
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
oan22_x1
2.7
80
4.40
1.22
22.6
4.7f
87
2.97
112
2.31
oan22_x2
2.7
80
4.40
1.93
35.7
6.6f
89
1.52
113
1.22
oan22_x1
Effort
FO4
Log.
a1
/\
¯_
2.50
a2
/\
¯_
2.36
b1
/\
¯_
2.34
b2
/\
¯_
2.14
oan22_x2
Effort
FO4
Log.
a1
/\
¯_
2.31
a2
/\
¯_
2.16
b1
/\
¯_
2.13
b2
/\
¯_
1.96
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 28 MAY 2007