cgi2 standard cell family

carry generator inverting
cgi2 symbol
The output is the inverted carry of bits a and b and carry input c, with the delay from pin c being favoured. The cells here use a P/N ratio of 2.
z:((a*b)+(a*c)+(b*c))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
cgi2_x05 2.3  70 3.85  0.67  10.2  3.3f  59  5.85  54  4.09
cgi2_x1 2.3  70 3.85 1.32  18.6  5.9f  57  3.00  51  2.04
cgi2_x2 4.3 130 7.15 2.48  35.7 10.6f  57  1.58  52  1.10
cgi2_x05
 
Effort
FO4 Log.
a /\ 2.76 3.55
¯_
b /\ 2.72 3.53
¯_
c /\ 1.74 1.91
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cgi2_x05 schematic cgi2_x05 standard cell layout
cgi2_x1
 
Effort
FO4 Log.
a /\ 2.62 3.38
¯_
b /\ 2.57 3.34
¯_
c /\ 1.62 1.72
¯_
cgi2_x1 schematic cgi2_x1 standard cell layout
cgi2_x2
 
Effort
FO4 Log.
a /\ 2.74 3.61
¯_
b /\ 2.52 3.26
¯_
c /\ 1.59 1.65
¯_
cgi2_x2 schematic cgi2_x2 standard cell layout