a2 standard cell family
2-I/P AND gate
UP
PREV
NEXT
2 I/P AND gate with a stage effort of about 1.8 for the a2_x2 and about 3.6 for the a2_x4.
q:(i1*i0)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i0
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
a2_x2
1.7
50
2.75
1.16
30.0
5.2f
72
1.52
98
1.20
a2_x4
2.0
60
3.30
2.08
45.6
4.7f
91
0.76
121
0.61
a2_x2
Effort
FO4
Log.
i0
/\
¯_
1.61
i1
/\
¯_
1.75
a2_x4
Effort
FO4
Log.
i0
/\
¯_
1.70
i1
/\
¯_
1.80
Web data book for the ssxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 16 JUL 2007