xaoi21 standard cell family

2-I/P exclusive NOR gate with 2-AND input
xaoi21 symbol
2 XNOR gates with AND gate input designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1*a2)^b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xaoi21_x05 2.7  80 4.40  0.70  24.1  4.2f 102  4.77  98  3.89
xaoi21_x1 3.0  90 4.95 1.35  41.4  7.3f  94  2.50  90  2.01
xaoi21_x05
 
Effort
FO4 Log.
a1 /\ 2.11 1.80
¯_ 2.95
a2 /\ 2.04 1.73
¯_ 2.88
b /\ 2.06 2.57
¯_ 2.55
xaoi21_x05 schematic xaoi21_x05 standard cell layout
xaoi21_x1
 
Effort
FO4 Log.
a1 /\ 1.90 1.59
¯_ 2.73
a2 /\ 1.84 1.53
¯_ 2.68
b /\ 1.92 2.42
¯_ 2.32
xaoi21_x1 schematic xaoi21_x1 standard cell layout