na3 standard cell family
3-I/P NAND gate
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The na3_x1 is a single stage 3-NAND with P/N ratio of about 2.3, which makes the P and N transistors the same size. The na3_x4 is a 3 stage 3-NAND with stage efforts of about 1.1 and 3.9.
nq:(i0*i1*i2)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i2
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
na3_x1
1.7
50
2.75
0.92
12.6
5.4f
55
2.97
44
2.54
na3_x4
2.7
80
4.40
2.66
65.5
5.6f
166
0.74
163
0.57
na3_x1
Effort
FO4
Log.
i0
/\
1.63
1.63
¯_
i1
/\
1.63
1.73
¯_
i2
/\
1.55
1.71
¯_
na3_x4
Effort
FO4
Log.
i0
/\
2.44
0.40
¯_
i1
/\
2.65
0.44
¯_
i2
/\
2.56
0.42
¯_
Web data book for the sxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 08 JUL 2007