aon21 standard cell family
2-AND into 2-OR gate
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2 cells with different drive strengths, each with a P:N ratio of about 2. The aon21_x1 has a stage effort of about 1.7 and the aon21_x2 about 2.2.
z:((a1*a2)+b)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
a2
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
aon21_x1
2.3
70
3.85
0.92
24.5
4.7f
95
2.98
113
2.29
aon21_x2
2.3
70
3.85
1.41
38.7
6.4f
98
1.57
116
1.21
aon21_x1
Effort
FO4
Log.
a1
/\
¯_
2.25
a2
/\
¯_
2.19
b
/\
¯_
1.87
aon21_x2
Effort
FO4
Log.
a1
/\
¯_
2.10
a2
/\
¯_
2.04
b
/\
¯_
1.73
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 28 MAY 2007