nr2 standard cell family
2-I/P NOR gate
UP
PREV
NEXT
The P/N ratio has been kept as close to 2 as possible for balanced output skew, even if this is not the fastest configuration.
z:(a+b)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
b
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nr2_x05
1.3
40
2.20
0.32
5.8
3.1f
45
5.28
44
3.81
nr2_x1
1.3
40
2.20
0.70
9.4
5.2f
44
2.98
42
2.08
nr2_x2
2.0
60
3.30
1.39
16.4
9.7f
41
1.49
40
1.09
nr2_x05
Effort
FO4
Log.
a
/\
1.62
1.73
¯_
b
/\
1.44
1.64
¯_
nr2_x1
Effort
FO4
Log.
a
/\
1.52
1.60
¯_
b
/\
1.35
1.51
¯_
nr2_x2
Effort
FO4
Log.
a
/\
1.50
1.58
¯_
b
/\
1.30
1.45
¯_
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 28 MAY 2007