nd3a standard cell family
3-I/P NAND gate with inverted input
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Minimum size 3-I/P NAND gate with an inverted input. The output P/N ratio is about 2.3, and the gain from input
a
is about 1.3.
z:(a'*b*c)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
c
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nd3av0x05
2.3
56
3.08
0.67
5.9
2.5f
53
5.94
42
5.09
nd3av0x05
Effort
FO4
Log.
a
/\
¯_
2.19
b
/\
1.58
1.67
¯_
c
/\
1.46
1.57
¯_
Web data book for the vsclib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 05 JUL 2007