o3 standard cell family
3-I/P OR gate
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3 I/P OR gate with a stage effort of about 2.8 for the o3_x2 and about 5.7 for the o3_x4.
q:(i0+i1+i2)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i2
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
o3_x2
2.0
60
3.30
1.39
32.2
4.6f
86
1.52
154
1.25
o3_x4
2.3
70
3.85
2.08
48.4
4.4f
103
0.76
198
0.65
o3_x2
Effort
FO4
Log.
i0
/\
¯_
2.47
i1
/\
¯_
2.34
i2
/\
¯_
2.08
o3_x4
Effort
FO4
Log.
i0
/\
¯_
2.77
i1
/\
¯_
2.58
i2
/\
¯_
2.33
Web data book for the ssxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 16 JUL 2007