a4 standard cell family

4-I/P AND gate
a4 symbol
4 I/P AND gate designed with a stage effort of about 2.4 for the a4_x2 and about 4.8 for the a4_x4.
q:(i0*i1*i2*i3) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i3.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
a4_x2 2.3  70 3.85 1.85  34.5  5.1f 117  1.57 114  1.21
a4_x4 2.7  80 4.40 2.54  50.3  4.9f 142  0.80 137  0.61
a4_x2
 
Effort
FO4 Log.
i0 /\
¯_ 2.30
i1 /\
¯_ 2.26
i2 /\
¯_ 2.16
i3 /\
¯_ 2.05
a4_x2 schematic a4_x2 standard cell layout
a4_x4
 
Effort
FO4 Log.
i0 /\
¯_ 2.44
i1 /\
¯_ 2.38
i2 /\
¯_ 2.31
i3 /\
¯_ 2.19
a4_x4 schematic a4_x4 standard cell layout